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publication number s29jl032j_00 revision 06 issue date december 16, 2011 s29jl032j s29jl032j cover sheet 32 megabit (4m x 8-bit/2m x 16-bit) cmos 3.0 volt-only, simultaneous read/write flash memory data sheet notice to readers: this document states the current techni cal specifications regarding the spansion product(s) described herein. each product described herein may be designated as advance information, preliminary, or full production. see notice on data sheet designations for definitions.
2 s29jl032j s29jl032j_00_06 december 16, 2011 data sheet notice on data sheet designations spansion inc. issues data sheets with advance informat ion or preliminary designati ons to advise readers of product information or intended s pecifications throughout the produc t life cycle, including development, qualification, initial production, and full production. in all cases, however, reader s are encouraged to verify that they have the latest information before finalizi ng their design. the following descriptions of spansion data sheet designations are presented here to hi ghlight their presenc e and definitions. advance information the advance information designation i ndicates that spansion inc. is de veloping one or more specific products, but has not committed any des ign to production. information pr esented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spansion inc. therefore plac es the following conditions upo n advance information content: ?this document contains information on one or more products under development at spansion inc. the information is intended to help you evaluate this product. do not design in this product without contacting the factory. spansion inc. reserves the right to change or discontinue work on this proposed product without notice.? preliminary the preliminary designation indicates that the product development has pr ogressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these aspects of production under c onsideration. spansion places the following conditi ons upon preliminary content: ?this document states the current technical specifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.? combination some data sheets contain a combination of products with different designati ons (advance information, preliminary, or full production). th is type of document distinguishes t hese products and their designations wherever necessary, typically on the first page, th e ordering information page, and pages with the dc characteristics table and the ac er ase and program table (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of ti me such that no changes or only nominal changes are expected, the preliminary desi gnation is removed from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as the a ddition or deletion of a speed option, temperat ure range, package type, or v io range. changes may also include those needed to clarify a description or to correct a typographic al error or incorrect specificati on. spansion inc. applies the following conditions to documents in this category: ?this document states the current technical specifications regarding the spansion product(s) described herein. spansion inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or modifications to the valid combinations offered may occur.? questions regarding these document designations may be directed to your local sales office.
publication number s29jl032j_00 revision 06 issue date december 16, 2011 distinctive characteristics architectural advantages ? simultaneous read/write operations ? data can be continuously read from one bank while executing erase/program functions in another bank. ? zero latency between read and write operations ? multiple bank architecture ? four bank architectures available (refer to table 8.2 on page 17 ). ? boot sectors ? top or bottom boot sector configurations available ? any combination of sectors can be erased ? manufactured on 0.11 m process technology ? secured silicon region: extra 256 byte sector ? factory locked and identifiable: 16 bytes available for secure, random factory electronic serial number; verifiable as factory locked through autoselect function ? customer lockable: one-time programmable only. once locked, data cannot be changed ? zero power operation ? sophisticated power management circuits reduce power consumed during inactive periods to nearly zero. ? compatible with jedec standards ? pinout and software compatible with single-power-supply flash standard package options ? 48-ball fine-pitch bga ? 48-pin tsop performance characteristics ? high performance ? access time as fast as 60 ns ? program time: 6 s/word typical using accelerated programming function ? ultra low power consumption (typical values) ? 2 ma active read current at 1 mhz ? 10 ma active read current at 5 mhz ? 200 na in standby or automatic sleep mode ? cycling endurance: 1 million cycles per sector typical ? data retention: 20 years typical software features ? supports common flash memory interface (cfi) ? erase suspend/erase resume ? suspends erase operations to read data from, or program data to, a sector that is not being erased, then resumes the erase operation. ? data# polling and toggle bits ? provides a software method of detecting the status of program or erase operations ? unlock bypass program command ? reduces overall programming time when issuing multiple program command sequences hardware features ? ready/busy# output (ry/by#) ? hardware method for detecting program or erase cycle completion ? hardware reset pin (reset#) ? hardware method of resetting the internal state machine to the read mode ? wp#/acc input pin ? write protect (wp#) function protects the two outermost boot sectors regardless of sector protect status ? acceleration (acc) function accelerates program timing ? sector protection ? hardware method to prevent any program or erase operation within a sector ? temporary sector unprotect allows changing data in protected sectors in-system general description the s29jl032j is a 32 mbit, 3.0 volt-only fl ash memory device, organized as 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits each. word mode data appears on dq15?dq0; byte mode data appears on dq7?dq0. the device is designed to be programmed in-system wi th the standard 3.0 volt v cc supply, and can also be programmed in standard eprom programmers. the device is available with an access time of 60, or 70 ns and is offe red in a 48-ball fbga or a 48-pin tsop package. standard control pins?chip enabl e (ce#), write enable (we#), and outp ut enable (oe#)?control normal read and write operations, and avoid bus contention issues. the device r equires only a single 3. 0 volt power supply for both read and write functions. internally generated and regulated vo ltages are provided for the program and erase operations. s29jl032j 32 megabit (4m x 8-bit/2m x 16-bit) cmos 3.0 volt-only, simultaneous read/write flash memory data sheet
4 s29jl032j s29jl032j_00_06 december 16, 2011 data sheet table of contents distinctive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1. simultaneous read/write operations with zero latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 s29jl032j features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2. product selector guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 4-bank device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 2-bank device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4. connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 48-pin tsop package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 48-ball fbga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6. logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8. device bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.1 word/byte configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.2 requirements for reading array data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.3 writing commands/command sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.4 simultaneous read/write oper ations with zero latency . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.5 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.6 automatic sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.7 reset#: hardware reset pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 8.8 output disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.9 autoselect mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.10 boot sector/sector block protection and unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.11 write protect (wp#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.12 temporary sector unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.13 secured silicon region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.14 hardware data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9. common flash memory interface (cfi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 10. command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10.1 reading array data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10.2 reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10.3 autoselect command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.4 enter secured silicon region/exit secured si licon region command sequence . . . . . . . . 33 10.5 byte/word program command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.6 chip erase command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.7 sector erase command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.8 erase suspend/erase resume commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11. write operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11.1 dq7: data# polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11.2 ry/by#: ready/busy#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11.3 dq6: toggle bit i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11.4 dq2: toggle bit ii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11.5 reading toggle bits dq6/dq2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11.6 dq5: exceeded timing limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11.7 dq3: sector erase timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 12. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 13. operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 14. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 14.1 cmos compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
december 16, 2011 s29jl032j_00_06 s29jl032j 5 data sheet 14.2 zero-power flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 15. test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 16. key to switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 17. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 17.1 read-only operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 17.2 hardware reset (reset#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 17.3 word/byte configuration (byte#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 0 17.4 erase and program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 17.5 temporary sector unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 17.6 alternate ce# controlled erase and pr ogram operations . . . . . . . . . . . . . . . . . . . . . . . . . . 56 18. erase and programming performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 19. pin capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 20. physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 20.1 ts 048?48-pin standard tsop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 20.2 vbk048?48-pin fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 21. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6 s29jl032j s29jl032j_00_06 december 16, 2011 data sheet figures figure 8.1 temporary sector unprotect operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 8.2 in-system sector protect/unprotect algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 8.3 secured silicon region protect verify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 10.1 program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 10.2 erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 11.1 data# polling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 11.2 toggle bit algor ithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 12.1 maximum negative overshoot waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 12.2 maximum positive overshoot waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 figure 14.1 i cc1 current vs. time (showing active and automatic sle ep currents) . . . . . . . . . . . . . . . . 46 figure 14.2 typical i cc1 vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 15.1 test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 16.1 input waveforms and measurement levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 17.1 read operation timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 17.2 reset timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 17.3 byte# timings for read operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 17.4 byte# timings for write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 17.5 program operation timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 17.6 accelerated program timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 17.7 chip/sector erase operation timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 17.8 back-to-back read/write cycle timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 17.9 data# polling timing s (during embedded algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 17.10 toggle bit timi ngs (during embedded algorithms). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 17.11 dq2 vs. dq6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 17.12 temporary sector unprotect timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 figure 17.13 sector/sector block protect and unprotect timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 17.14 alternate ce# controlled write (erase/program) operation timings . . . . . . . . . . . . . . . . . . 57
december 16, 2011 s29jl032j_00_06 s29jl032j 7 data sheet tables table 8.1 s29jl032j device bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 8.2 s29jl032j bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 8.3 s29jl032j sector addresses - top boot devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 8.4 s29jl032j sector addresses - bottom boot devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8.5 s29jl032j autoselect codes (high voltage method). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 8.6 s29jl032j boot sector /sector block addresses for protection/unprotection (top boot devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 8.7 s29jl032j sector/sector block addresses for protection/unprotection (bottom boot devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 8.8 wp#/acc modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 9.1 cfi query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 9.2 system interface string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 9.3 device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 9.4 primary vendor-specific extended query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 table 10.1 s29jl032j command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 11.1 write operation status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 15.1 test specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8 s29jl032j s29jl032j_00_06 december 16, 2011 data sheet 1. simultaneous read/write op erations with zero latency the simultaneous read/write architecture provides simultaneous operation by dividing the memory space into separate banks (see table 8.2 on page 17 ). sector addresses are fixed, system software can be used to form user-defined bank groups. during an erase/program operation, any of the non-busy banks may be read from. note that only two banks can operate simultaneously. the device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simu ltaneously read from the other bank, with zero latency. this releases the system from waiting fo r the completion of progra m or erase operations. the s29jl032j can be organized with either a top or bottom boot sect or configuration. 1.1 s29jl032j features the secured silicon region is an extra 256 byte sector capabl e of being permanently locked by the customer. the secured silicon customer indicator bi t (dq6) is permanently set to 1 if the part has been locked and is 0 if lockable. customers may utilize the secured s ilicon region as bonus space, readin g and writing like any other flash sector, or may permanently lock their own code there. the device offers complete compatibility with the jedec 42.4 single-power-su pply flash command set standard . commands are written to the command register using standard micropr ocessor write timings. reading data out of the device is similar to reading from other fl ash or eprom devices. the host system can detect whether a program or erase operation is complete by using the device status bits: ry/by# pin, dq7 (data# polling) and dq6/dq2 (toggl e bits). after a program or erase cycle has been completed, the device automatic ally returns to the read mode. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully eras ed when shipped from the factory. hardware data protection measures include a low v cc detector that automatically inhibits write operations during power transitions. the hardware sector protection feature disables both program and erase operations in any combination of t he sectors of memory. this can be ac hieved in-system or via programming equipment. the erase suspend/erase resume feature enables the user to put eras e on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. true background erase can thus be achieved. if a read is needed from the secured silicon regi on area (one time pr ogram area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. the device offers two power-saving features. when add resses have been stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode . power consumption is greatly reduced in both modes.
december 16, 2011 s29jl032j_00_06 s29jl032j 9 data sheet 2. product selector guide 3. block diagram 3.1 4-bank device part number s29jl032j speed option standard voltage range: v cc = 3.0?3.6v 60 standard voltage range: v cc = 2.7?3.6v 70 max access time (ns), t acc 60 70 ce# access (ns), t ce 60 70 oe# access (ns), t oe 25 30 v cc v ss bank 1 address bank 2 address a20?a0 reset# we# ce# byte# dq0?dq15 wp#/acc state control & command register ry/by# bank 1 x-decoder oe# byte# dq15?dq0 status control a20?a0 a20?a0 a20?a0 a20?a0 dq15?dq0 dq15?dq0 dq15?dq0 dq15?dq0 mux mux mux bank 2 x-decoder y-gate bank 3 x-decoder bank 4 x-decoder y-gate bank 3 address bank 4 address
10 s29jl032j s29jl032j_00_06 december 16, 2011 data sheet 3.2 2-bank device v cc v ss upper bank address a20?a0 reset# we# ce# byte# dq15?dq0 wp#/acc state control & command register ry/by# upper bank x-decoder y-decoder latches and control logic oe# byte# dq15?dq0 lower bank y-decoder x-decoder latches and control logic lower bank address oe# byte# status control a20?a0 a20?a0 a20?a0 a20?a0 dq15?dq0 dq15?dq0
december 16, 2011 s29jl032j_00_06 s29jl032j 11 data sheet 4. connection diagrams 4.1 48-pin tsop package 4.2 48-ball fbga package 1 16 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 48 33 47 46 45 44 43 42 41 40 39 38 37 36 35 34 25 32 31 30 29 28 27 26 a15 a18 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# reset# nc wp#/acc ry/by# a1 a17 a7 a6 a5 a4 a3 a2 a16 dq2 byte# v ss dq15/a-1 dq7 dq14 dq6 dq13 dq9 dq1 dq8 dq0 oe# v ss ce# a0 dq5 dq12 dq4 v cc dq11 dq3 dq10 48-pin standard tsop b3 c3 d3 e3 f3 g3 h3 b4 c4 d4 e4 f4 g4 h4 b5 c5 d5 e5 f5 g5 h5 b6 c6 d6 e6 f6 g6 h6 v ss dq15/a-1 byte# a16 a15 a14 a12 dq6 dq13 dq14 dq7 a11 a10 a8 dq4 v cc dq12 dq5 a19 nc reset# dq3 dq11 dq10 dq2 a20 a18 wp#/acc a3 a4 a5 a6 a13 a9 we# ry/by# b2 c2 d2 e2 f2 g2 h2 dq1 dq9 dq8 dq0 a5 a6 a17 a2 a7 b1 c1 d1 e1 f1 g1 h1 v ss oe# ce# a0 a1 a2 a4 a1 a3
12 s29jl032j s29jl032j_00_06 december 16, 2011 data sheet 5. pin description 6. logic symbol a20?a0 21 address pins dq14?dq0 15 data inputs/outputs (x16-only devices) dq15/a-1 dq15 (data input/output, word mode), a-1 (lsb address input, byte mode) ce# chip enable, active low oe# output enable, active low we# write enable, active low wp#/acc hardware write protect/acceleration pin. reset# hardware reset pin, active low byte# selects 8-bit or 16-bit mode, active low ry/by# ready/busy output, active low v cc 3.0 volt-only single power supply (see product selector guide on page 9 for speed options and voltage supply tolerances) v ss device ground nc not connected ? no device internal signal is connected to the package connector nor is there any future plan to use the connector for a signal. the connection may safely be used for routing space for a signal on a printed circuit board (pcb). 21 16 or 8 dq15?dq0 (a-1) a20?a0 ce# oe# we# reset# byte# ry/by# wp#/acc
december 16, 2011 s29jl032j_00_06 s29jl032j 13 data sheet 7. ordering information the order number (valid combinatio n) is formed by the following: note: 1. type 0 is standard. specify others as required. valid combinations valid combinations list c onfigurations planned to be s upported in volume for this device. consult your local spansion sales office to confirm availability of specif ic valid combinations and to check on newly released combinations. s29jl032j 60 t f i 01 0 packing type 0=tray 3 = 13-inch tape and reel model number 01 = top boot device, 4 banks: 4/12/12/4 mb 02 = bottom boot device, 4 banks: 4/12/12/4 mb 21 = top boot device, 2 banks: 4/28 mb 22 = bottom boot device, 2 banks: 4/28 mb 31 = top boot device, 2 banks: 8/24 mb 32 = bottom boot device, 2 banks: 8/24 mb 41 = top boot device, 2 banks: 16/16 mb 42 = bottom boot device, 2 banks: 16/16 mb temperature range i = industrial (?40c to +85c) package material set f = pb-free h = low-halogen, pb-free package type b = fine-pitch ball grid array package t = thin small outline package (tsop) standard pinout speed option 60 = 60 ns 70 = 70 ns device family s29jl032j 3.0 volt-only, 32 mbit (2 m x 16-bit/4 m x 8-bit) simultaneous read/write flash memory manufactured on 110 nm process technology s29jl032j valid combinations device number/ description speed (ns) package type temperature range additional ordering options packing type package description s29jl032j 60, 70 tf i 01, 02, 21, 22, 31, 32, 41, 42 0, 3 (1) ts048 tsop bh 31, 32 vbk048 fbga
14 s29jl032j s29jl032j_00_06 december 16, 2011 data sheet 8. device bus operations this section describes the requirements and use of the device bus o perations, which are initiated through the internal command register. the comm and register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the addr ess and data information needed to execute the command. the cont ents of the register serve as inputs to the internal state machine. the state machine outputs dictate th e function of the device. table 8.1 lists the device bus oper ations, the inputs and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail. legend: l = logic low = v il h = logic high = v ih v id = 8.5?12.5v v hh = 9.0 0.5v x = don?t care sa = sector address a in = address in d in = data in d out = data out notes: 1. addresses are a20:a0 in word mode (byte# = v ih ), a20:a-1 in byte mode (byte# = v il ). 2. the sector protect and sector unprotect functions may also be implemented via programming equipment. see boot sector/sector block protection and unprotection on page 23 . 3. if wp#/acc = v il , the two outermost boot sectors remain protected. if wp#/acc = v ih , protection on the two outermost boot sectors depends on whether they were last protected or unprotected using the method described in boot sector/sector block protection and unprotection on page 23 . if wp#/acc = v hh , all sectors will be unprotected. 8.1 word/byte configuration the byte# pin controls whether the de vice data i/o pins operate in the by te or word config uration. if the byte# pin is set at logic ?1?, the device is in word configuration, dq15?d q0 are active and controlled by ce# and oe#. if the byte# pin is set at logic ?0?, the device is in byte configuration, and only data i/o pins dq7?dq0 are active and controlled by ce# and oe#. the data i/o pi ns dq14?dq8 are tri-stated , and the dq15 pin is used as an input for the lsb (a-1) address function. table 8.1 s29jl032j device bus operations operation ce# oe# we# reset# wp#/acc addresses (note 1) dq15?dq8 dq7?dq0 byte# = v ih byte# = v il read l l h h l/h a in d out dq14?dq8 = high-z, dq15 = a-1 d out write l h l h (note 3) a in d in d in standby v cc 0.3v xx v cc 0.3v l/h x high-z high-z high-z output disable l h h h l/h x high-z high-z high-z reset x x x l l/h x high-z high-z high-z sector protect (note 2) lhlv id l/h sa, a6 = l, a1 = h, a0 = l xxd in sector unprotect (note 2) lhlv id (note 3) sa, a6 = h, a1 = h, a0 = l xxd in temporary sector unprotect xxxv id (note 3) a in d in high-z d in
december 16, 2011 s29jl032j_00_06 s29jl032j 15 data sheet 8.2 requirements for reading array data to read array data from the outputs, the system mu st drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output control and ga tes array data to the output pins. we# should remain at v ih . the byte# pin determines w hether the device outputs array data in words or bytes. the internal state machine is set for reading array data upon device power-up, or af ter a hardware reset. this ensures that no spurious alteration of the memory c ontent occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles t hat assert valid addresses on the device address inputs produce valid data on th e device data outputs. each bank remains enabled for read access until the command r egister content s are altered. refer to the read-only operations on page 48 for timing specifications and to figure 17.1 on page 48 for the timing diagram. i cc1 in dc characteristics on page 45 represents the active curr ent specification for reading array data. 8.3 writing commands/command sequences to write a command or command sequence (which incl udes programming data to the device and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . for program operations, the byte# pin determines whet her the device accepts pr ogram data in bytes or words. refer to word/byte configuration on page 14 for more information. the device features an unlock bypass mode to facilitate faster progr amming. once a bank enters the unlock bypass mode, only two write cycles are requi red to program a word or byte, instead of four. byte/ word program command sequence on page 33 has details on programming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, multiple sector s, or the entire device. table 8.3 on page 18 and table 8.4 on page 20 indicate the address space that each sector occupies. similarly, a ?sector address? is the address bits required to uniquely select a sector. command definitions on page 32 has details on erasing a sector or the entire chip, or su spending/resuming the erase operation. the device address space is divided into four banks. a ?bank address? is the address bits required to uniquely select a bank. i cc2 in the dc characteristics table represents the active current specification for the write mode. ac characteristics on page 48 contains timing specification tables and timing diagrams for write operations. 8.3.1 accelerated program operation the device offers accelerated program operations throu gh the acc function. this is one of two functions provided by the wp#/acc pin. this function is primarily intended to allo w faster manufactur ing throughput at the factory. if the system asserts v hh on this pin, the device automatically enters the af orementioned unlock bypass mode, temporarily unprotects any pr otected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. the system wo uld use a two-cycle program command sequence as required by the unlock bypass mode. removing v hh from the wp#/acc pin returns the device to normal operation. note that v hh must not be asserted on wp#/acc for operations other than accelerated programming, or device damage may re sult. in addition, the wp#/acc pi n must not be left floating or unconnected; inconsistent behavior of the device may result. see write protect (wp#) on page 25 for related information. 8.3.2 autoselect functions if the system writes the autoselect command sequence , the device enters the aut oselect mode. the system can then read autoselect codes from th e internal register (which is se parate from the memory array) on dq15?dq0. standard read cycle timings apply in this mode. refer to autoselect mode on page 22 and autoselect command sequence on page 33 for more information.
16 s29jl032j s29jl032j_00_06 december 16, 2011 data sheet 8.4 simultaneous read/write op erations with zero latency this device is capable of reading data from one bank of memory while programming or erasing in another bank of memory. an erase operation may also be su spended to read from or pr ogram to another location within the same bank (except the sector being erased). figure 17.8 on page 53 shows how read and write cycles may be initiated for simultaneous operation with zero latency. i cc6 and i cc7 in dc characteristics on page 45 represent the current specifications for read-w hile-program and read-while-erase, respectively. 8.5 standby mode when the system is not reading or writ ing to the device, it can place the device in the standby mode. in this mode, current consumption is grea tly reduced, and the out puts are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when th e ce# and reset# pins are both held at v cc 0.3v. note that this is a more restricted voltage range than v ih . if ce# and reset# are held at v ih , but not within v cc 0.3v, the device will be in the standby mode, but the standby current will be greater. the device requires standard access time (t ce ) for read access when the device is in either of th ese standby modes, before it is ready to read data. if the device is deselected during er asure or programming, t he device draws active cu rrent until the operation is completed. i cc3 in dc characteristics on page 45 represents the standby current specification. 8.6 automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. the device automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signal s. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. i cc5 in dc characteristics on page 45 represents the automatic sl eep mode current specification. 8.7 reset#: hardware reset pin the reset# pin provides a hardware method of rese tting the device to read ing array data. when the reset# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, an d ignores all read/write commands fo r the duration of the reset# pulse. the device also resets the internal state machine to reading array data. the oper ation that was interrupted should be reinitiated once the device is ready to ac cept another command sequence, to ensure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.3v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.3v, the standby current will be greater. the reset# pin may be tied to the system reset circuitr y. a system reset would thus also reset the flash memory, enabling the system to read the b oot-up firmware from the flash memory. if reset# is asserted during a progra m or erase operation, the ry/by# pin remains a ?0? (busy) until the internal reset operation is complete, which requires a time of t ready (during embedded algorithms). the system can thus monitor ry/by# to determine whether the reset operation is complete. if reset# is asserted when a program or erase operation is not executing (ry/by# pin is ?1?), the reset operation is completed within a time of t ready (not during embedded algorithms). the system can read data t rh after the reset# pin returns to v ih . refer to hardware reset (reset#) on page 49 for reset# parameters and to figure 17.2 on page 49 for the timing diagram.
december 16, 2011 s29jl032j_00_06 s29jl032j 17 data sheet 8.8 output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high impedance state. table 8.2 s29jl032j bank architecture device model number bank 1 bank 2 bank 3 bank 4 mbit sector size mbit sector size mbit sector size mbit sector size 01, 02 4 mbit eight 8kbyte/ 4kword, seven 64 kbyte/ 32 kword 12 mbit twenty-four 64 kbyte/ 32 kword 12 mbit twenty-four 64 kbyte/ 32 kword 4mbit eight 64 kbyte/ 32 kword device model number bank 1 bank 2 mbits sector size mbit sector size 21, 22 4 mbit eight 8 kbyte/4 kword, seven 64 kbyte/32 kword 28 mbit fifty-six 64 kbyte/32 kword 31, 32 8 mbit eight 8 kbyte/4 kword, fifteen 64 kbyte/32 kword 24 mbit forty-eight 64 kbyte/32 kword 41, 42 16 mbit eight 8 kbyte/4 kword, thirty-one 64 kbyte/32 kword 16 mbit thirty-two 64 kbyte/32 kword
18 s29jl032j s29jl032j_00_06 december 16, 2011 data sheet table 8.3 s29jl032j sector addresses - top boot devices (sheet 1 of 2) s29jl032j (model 41) s29jl032j (model 31) s29jl032j (model 21) s29jl032j (model 01) sector sector address a20?a12 sector size (kbytes/kwords) (x8) address range (x16) address range bank 2 bank 2 bank 2 bank 4 sa0 000000xxx 64/32 000000h-00ffffh 000000h-07fffh sa1 000001xxx 64/32 010000h-01ffffh 008000h-0ffffh sa2 000010xxx 64/32 020000h-02ffffh 010000h-17fffh sa3 000011xxx 64/32 030000h-03ffffh 018000h-01ffffh sa4 000100xxx 64/32 040000h-04ffffh 020000h-027fffh sa5 000101xxx 64/32 050000h-05ffffh 028000h-02ffffh sa6 000110xxx 64/32 060000h-06ffffh 030000h-037fffh sa7 000111xxx 64/32 070000h-07ffffh 038000h-03ffffh bank 3 sa8 001000xxx 64/32 080000h-08ffffh 040000h-047fffh sa9 001001xxx 64/32 090000h-09ffffh 048000h-04ffffh sa10 001010xxx 64/32 0a0000h-0affffh 050000h-057fffh sa11 001011xxx 64/32 0b0000h-0bffffh 058000h-05ffffh sa12 001100xxx 64/32 0c0000h-0cffffh 060000h-067fffh sa13 001101xxx 64/32 0d0000h-0dffffh 068000h-06ffffh sa14 001110xxx 64/32 0e0000h-0effffh 070000h-077fffh sa15 001111xxx 64/32 0f0000h-0fffffh 078000h-07ffffh sa16 010000xxx 64/32 100000h-10ffffh 080000h-087fffh sa17 010001xxx 64/32 110000h-11ffffh 088000h-08ffffh sa18 010010xxx 64/32 120000h-12ffffh 090000h-097fffh sa19 010011xxx 64/32 130000h-13ffffh 098000h-09ffffh sa20 010100xxx 64/32 140000h-14ffffh 0a0000h-0a7fffh sa21 010101xxx 64/32 150000h-15ffffh 0a8000h-0affffh sa22 010110xxx 64/32 160000h-16ffffh 0b0000h-0b7fffh sa23 010111xxx 64/32 170000h-17ffffh 0b8000h-0bffffh sa24 011000xxx 64/32 180000h-18ffffh 0c0000h-0c7fffh sa25 011001xxx 64/32 190000h-19ffffh 0c8000h-0cffffh sa26 011010xxx 64/32 1a0000h-1affffh 0d0000h-0d7fffh sa27 011011xxx 64/32 1b0000h-1bffffh 0d8000h-0dffffh sa28 011100xxx 64/32 1c0000h-1cffffh 0e0000h-0e7fffh sa29 011101xxx 64/32 1d0000h-1dffffh 0e8000h-0effffh sa30 011110xxx 64/32 1e0000h-1effffh 0f0000h-0f7fffh sa31 011111xxx 64/32 1f0000h-1fffffh 0f8000h-0fffffh
december 16, 2011 s29jl032j_00_06 s29jl032j 19 data sheet bank 1 bank 2 (continued) bank 2 (continued) bank 2 sa32 100000xxx 64/32 200000h-20ffffh 100000h-107fffh sa33 100001xxx 64/32 210000h-21ffffh 108000h-10ffffh sa34 100010xxx 64/32 220000h-22ffffh 110000h-117fffh sa35 100011xxx 64/32 230000h-23ffffh 118000h-11ffffh sa36 100100xxx 64/32 240000h-24ffffh 120000h-127fffh sa37 100101xxx 64/32 250000h-25ffffh 128000h-12ffffh sa38 100110xxx 64/32 260000h-26ffffh 130000h-137fffh sa39 100111xxx 64/32 270000h-27ffffh 138000h-13ffffh sa40 101000xxx 64/32 280000h-28ffffh 140000h-147fffh sa41 101001xxx 64/32 290000h-29ffffh 148000h-14ffffh sa42 101010xxx 64/32 2a0000h-2affffh 150000h-157fffh sa43 101011xxx 64/32 2b0000h-2bffffh 158000h-15ffffh sa44 101100xxx 64/32 2c0000h-2cffffh 160000h-167fffh sa45 101101xxx 64/32 2d0000h-2dffffh 168000h-16ffffh sa46 101110xxx 64/32 2e0000h-2effffh 170000h-177fffh sa47 101111xxx 64/32 2f0000h-2fffffh 178000h-17ffffh bank 1 sa48 110000xxx 64/32 300000h-30ffffh 180000h-187fffh sa49 110001xxx 64/32 310000h-31ffffh 188000h-18ffffh sa50 110010xxx 64/32 320000h-32ffffh 190000h-197fffh sa51 110011xxx 64/32 330000h-33ffffh 198000h-19ffffh sa52 110100xxx 64/32 340000h-34ffffh 1a0000h-1a7fffh sa53 110101xxx 64/32 350000h-35ffffh 1a8000h-1affffh sa54 110110xxx 64/32 360000h-36ffffh 1b0000h-1bffffh sa55 110111xxx 64/32 370000h-37ffffh 1b8000h-1bffffh bank 1 bank 1 sa56 111000xxx 64/32 380000h-38ffffh 1c0000h-1c7fffh sa57 111001xxx 64/32 390000h-39ffffh 1c8000h-1cffffh sa58 111010xxx 64/32 3a0000h-3affffh 1d0000h-1dffffh sa59 111011xxx 64/32 3b0000h-3bffffh 1d8000h-1dffffh sa60 111100xxx 64/32 3c0000h-3cffffh 1e0000h-1e7fffh sa61 111101xxx 64/32 3d0000h-3dffffh 1e8000h-1effffh sa62 111110xxx 64/32 3e0000h-3effffh 1f0000h-1f7fffh sa63 111111000 8/4 3f0000h-3f1fffh 1f8000h-1f8fffh sa64 111111001 8/4 3f2000h-3f3fffh 1f9000h-1f9fffh sa65 111111010 8/4 3f4000h-3f5fffh 1fa000h-1fafffh sa66 111111011 8/4 3f6000h-3f7fffh 1fb000h-1fbfffh sa67 111111100 8/4 3f8000h-3f9fffh 1fc000h-1fcfffh sa68 111111101 8/4 3fa000h-3fbfffh 1fd000h-1fdfffh sa69 111111110 8/4 3fc000h-3fdfffh 1fe000h-1fefffh sa70 111111111 8/4 3fe000h-3fffffh 1ff000h-1fffffh table 8.3 s29jl032j sector addresses - top boot devices (sheet 2 of 2) s29jl032j (model 41) s29jl032j (model 31) s29jl032j (model 21) s29jl032j (model 01) sector sector address a20?a12 sector size (kbytes/kwords) (x8) address range (x16) address range
20 s29jl032j s29jl032j_00_06 december 16, 2011 data sheet table 8.4 s29jl032j sector addresses - bott om boot devices (sheet 1 of 2) s29jl032j (model 42) s29jl032j (model 32) s29jl032j (model 22) s29jl032j (model 02) sector sector address a20?a12 sector size (kbytes/kwords) (x8) address range (x16) address range bank 1 bank 1 bank 1 bank 1 sa0 000000000 8/4 000000h-001fffh 000000h-000fffh sa1 000000001 8/4 002000h-003fffh 001000h-001fffh sa2 000000010 8/4 004000h-005fffh 002000h-002fffh sa3 000000011 8/4 006000h-007fffh 003000h-003fffh sa4 000000100 8/4 008000h-009fffh 004000h-004fffh sa5 000000101 8/4 00a000h-00bfffh 005000h-005fffh sa6 000000110 8/4 00c000h-00dfffh 006000h-006fffh sa7 000000111 8/4 00e000h-00ffffh 007000h-007fffh sa8 000001xxx 64/32 010000h-01ffffh 008000h-00ffffh sa9 000010xxx 64/32 020000h-02ffffh 010000h-017fffh sa10 000011xxx 64/32 030000h-03ffffh 018000h-01ffffh sa11 000100xxx 64/32 040000h-04ffffh 020000h-027fffh sa12 000101xxx 64/32 050000h-05ffffh 028000h-02ffffh sa13 000110xxx 64/32 060000h-06ffffh 030000h-037fffh sa14 000111xxx 64/32 070000h-07ffffh 038000h-03ffffh bank 2 bank 2 sa15 001000xxx 64/32 080000h-08ffffh 040000h-047fffh sa16 001001xxx 64/32 090000h-09ffffh 048000h-04ffffh sa17 001010xxx 64/32 0a0000h-0affffh 050000h-057fffh sa18 001011xxx 64/32 0b0000h-0bffffh 058000h-05ffffh sa19 001100xxx 64/32 0c0000h-0cffffh 060000h-067fffh sa20 001101xxx 64/32 0d0000h-0dffffh 068000h-06ffffh sa21 001110xxx 64/32 0e0000h-0effffh 070000h-077fffh sa22 001111xxx 64/32 0f0000h-0fffffh 078000h-07ffffh bank 2 sa23 010000xxx 64/32 100000h-10ffffh 080000h-087fffh sa24 010001xxx 64/32 110000h-11ffffh 088000h-08ffffh sa25 010010xxx 64/32 120000h-12ffffh 090000h-097fffh sa26 010011xxx 64/32 130000h-13ffffh 098000h-09ffffh sa27 010100xxx 64/32 140000h-14ffffh 0a0000h-0a7fffh sa28 010101xxx 64/32 150000h-15ffffh 0a8000h-0affffh sa29 010110xxx 64/32 160000h-16ffffh 0b0000h-0b7fffh sa30 010111xxx 64/32 170000h-17ffffh 0b8000h-0bffffh sa31 011000xxx 64/32 180000h-18ffffh 0c0000h-0c7fffh sa32 011001xxx 64/32 190000h-19ffffh 0c8000h-0cffffh sa33 011010xxx 64/32 1a0000h-1affffh 0d0000h-0d7fffh sa34 011011xxx 64/32 1b0000h-1bffffh 0d8000h-0dffffh sa35 011100xxx 64/32 1c0000h-1cffffh 0e0000h-0e7fffh sa36 011101xxx 64/32 1d0000h-1dffffh 0e8000h-0effffh sa37 011110xxx 64/32 1e0000h-1effffh 0f0000h-0f7fffh sa38 011111xxx 64/32 1f0000h-1fffffh 0f8000h-0fffffh
december 16, 2011 s29jl032j_00_06 s29jl032j 21 data sheet bank 2 bank 2 (continued) bank 2 (continued) bank 3 sa39 100000xxx 64/32 200000h-20ffffh 100000h-107fffh sa40 100001xxx 64/32 210000h-21ffffh 108000h-10ffffh sa41 100010xxx 64/32 220000h-22ffffh 110000h-117fffh sa42 100011xxx 64/32 230000h-23ffffh 118000h-11ffffh sa43 100100xxx 64/32 240000h-24ffffh 120000h-127fffh sa44 100101xxx 64/32 250000h-25ffffh 128000h-12ffffh sa45 100110xxx 64/32 260000h-26ffffh 130000h-137fffh sa46 100111xxx 64/32 270000h-27ffffh 138000h-13ffffh sa47 101000xxx 64/32 280000h-28ffffh 140000h-147fffh sa48 101001xxx 64/32 290000h-29ffffh 148000h-14ffffh sa49 101010xxx 64/32 2a0000h-2affffh 150000h-157fffh sa50 101011xxx 64/32 2b0000h-2bffffh 158000h-15ffffh sa51 101100xxx 64/32 2c0000h-2cffffh 160000h-167fffh sa52 101101xxx 64/32 2d0000h-2dffffh 168000h-16ffffh sa53 101110xxx 64/32 2e0000h-2effffh 170000h-177fffh sa54 111111xxx 64/32 2f0000h-2fffffh 178000h-17ffffh sa55 111000xxx 64/32 300000h-30ffffh 180000h-187fffh sa56 110001xxx 64/32 310000h-31ffffh 188000h-18ffffh sa57 110010xxx 64/32 320000h-32ffffh 190000h-197fffh sa58 110011xxx 64/32 330000h-33ffffh 198000h-19ffffh sa59 110100xxx 64/32 340000h-34ffffh 1a0000h-1a7fffh sa60 110101xxx 64/32 350000h-35ffffh 1a8000h-1affffh sa61 110110xxx 64/32 360000h-36ffffh 1b0000h-1b7fffh sa62 110111xxx 64/32 370000h-37ffffh 1b8000h-1bffffh bank 4 sa63 111000xxx 64/32 380000h-38ffffh 1c0000h-1c7fffh sa64 111001xxx 64/32 390000h-39ffffh 1c8000h-1cffffh sa65 111010xxx 64/32 3a0000h-3affffh 1d0000h-1d7fffh sa66 111011xxx 64/32 3b0000h-3bffffh 1d8000h-1dffffh sa67 111100xxx 64/32 3c0000h-3cffffh 1e0000h-1e7fffh sa68 111101xxx 64/32 3d0000h-3dffffh 1e8000h-1effffh sa69 111110xxx 64/32 3e0000h-3effffh 1f0000h-1f7fffh sa70 111111xxx 64/32 3f0000h-3f1fffh 1f8000h-1fffffh table 8.4 s29jl032j sector addresses - bott om boot devices (sheet 2 of 2) s29jl032j (model 42) s29jl032j (model 32) s29jl032j (model 22) s29jl032j (model 02) sector sector address a20?a12 sector size (kbytes/kwords) (x8) address range (x16) address range
22 s29jl032j s29jl032j_00_06 december 16, 2011 data sheet 8.9 autoselect mode the autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on dq7?dq0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding pr ogramming algorithm. however, the autoselect codes can also be accessed in-system through th e command register. when using programming equipment, t he autoselect mode requires v id on address pin a9. address pins must be as shown in table 8.5 . in addition, when verifying sector pr otection, the sector address must appear on the appropriate highest order address bits. table 8.5 shows the remaining addre ss bits that are don?t care. when all necessary bits have been set as required, the programming equipm ent may then read the corresponding identifier code on dq7?dq0. however, t he autoselect codes can also be accessed in-system through the command register, for instances when the s29jl032j is erased or programmed in a system without access to high voltage on the a9 pin. the command sequence is illustrated in table 10.1 on page 38 . note that if a bank address (ba) on address bits a20, a19 and a18 is as serted during the third write cycle of the autoselect command, the host system can read autoselect data from th at bank and then immediately read array data from another bank, wi thout exiting t he autoselect mode. to access the autoselect codes in-system, the host system can issue the aut oselect command via the command register, as shown in table 10.1 on page 38 . this method does not require v id . refer to autoselect command sequence on page 33 for more information. legend: l = logic low = v il h = logic high = v ih ba = bank address sa = sector address x = don?t care . table 8.5 s29jl032j autoselect codes (high voltage method) description ce# oe# we# a20 to a12 a11 to a10 a9 a8 to a7 a6 a5 to a4 a3 a2 a1 a0 dq15 to dq8 dq7 to dq0 byte# = v ih byte# = v il manufacturer id : spansion products ll hbaxv id xlxllll x x 01h device id (models 01, 02) read cycle 1 ll hbaxv id x l x lllh 22h x 7eh read cycle 2 l h h h l 22h 0ah read cycle 3 l h h h h 22h 00h (bottom boot) 01h (top boot) device id (models 21, 22) ll hbaxv id xlxxxlh 22h x 56h (bottom boot) 55h (top boot) device id (models 31, 32) ll hbaxv id xlxxxlh 22h x 53h (bottom boot) 50h (top boot) device id (models 41, 42) ll hbaxv id xlxxxlh 22h x 5fh (bottom boot) 5ch (top boot) sector protection verification ll hsaxv id xlxllhl x x 01h (protected), 00h (unprotected) secured silicon indicator bit (dq6, dq7) ll hbaxv id xlxllhh x x 82h (factory locked), 42h (customer locked), 02h (not locked)
december 16, 2011 s29jl032j_00_06 s29jl032j 23 data sheet 8.10 boot sector/sector bloc k protection and unprotection note: for the following discussion, the term ?sector? ap plies to both boot sectors and sector blocks. a sector block consists of two or more adjac ent sectors that are pr otected or unprotected at the same time (see table 8.6 ). the hardware sector protection f eature disables both progr am and erase operations in any sector. the hardware sector unprotec tion feature re-enables both program and er ase operations in previously protected sectors. sector protec tion/unprotection can be impl emented via two methods. table 8.6 s29jl032j boot sector/sector block addresses for protection/unprotection (top boot devices) sector a20-a12 sector/ sector block size sa0 000000xxx 64 kbytes sa1-sa3 000001xxx 000010xxx 000011xxx 192 (3x64) kbytes sa4-sa7 0001xxxxx 256 (4x64) kbytes sa8-sa11 0010xxxxx 256 (4x64) kbytes sa12-sa15 0011xxxxx 256 (4x64) kbytes sa16-sa19 0100xxxxx 256 (4x64) kbytes sa20-sa23 0101xxxxx 256 (4x64) kbytes sa24-sa27 0110xxxxx 256 (4x64) kbytes sa28-sa31 0111xxxxx 256 (4x64) kbytes sa32-sa35 1000xxxxx 256 (4x64) kbytes sa36-sa39 1001xxxxx 256 (4x64) kbytes sa40-sa43 1010xxxxx 256 (4x64) kbytes sa44-sa47 1011xxxxx 256 (4x64) kbytes sa48-sa51 1100xxxxx 256 (4x64) kbytes sa52-sa55 1101xxxxx 256 (4x64) kbytes sa56-sa59 1110xxxxx 256 (4x64) kbytes sa60-sa62 111100xxx 111101xxx 111110xxx 192 (3x64) kbytes sa63 111111000 8 kbytes sa64 111111001 8 kbytes sa65 111111010 8 kbytes sa66 111111011 8 kbytes sa67 111111100 8 kbytes sa68 111111101 8 kbytes sa69 111111110 8 kbytes sa70 111111111 8 kbytes
24 s29jl032j s29jl032j_00_06 december 16, 2011 data sheet sector protect/sector unprotect requires v id on the reset# pin only, and can be implemented either in- system or via programming equipment. figure 8.2 on page 26 shows the algorithms and figure 17.13 on page 56 shows the timing diagram. for sect or unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. note that the sector unprotect algorithm unprotects all sectors in parallel. all previously protected sector s must be individually re-protect ed. to change data in protected sectors efficiently, the temporary sector unprotect function is available. see temporary sector unprotect on page 25. the device is shipped with all sectors unprotect ed. optional spansion programming service enable programming and protecting sectors at t he factory prior to shipping the device . contact your local sales office for details. it is possible to determi ne whether a sector is prot ected or unprotected. see autoselect mode on page 22 for details. table 8.7 s29jl032j sector/sector block addresses for protection/unprotection (bottom boot devices) sector a20-a12 sector/ sector block size sa70 111111xxx 64 kbytes sa69-sa67 111110xxx 111101xxx 111100xxx 192 (3x64) kbytes sa66-sa63 1110xxxxx 256 (4x64) kbytes sa62-sa59 1101xxxxx 256 (4x64) kbytes sa58-sa55 1100xxxxx 256 (4x64) kbytes sa54-sa51 1011xxxxx 256 (4x64) kbytes sa50-sa47 1010xxxxx 256 (4x64) kbytes sa46-sa43 1001xxxxx 256 (4x64) kbytes sa42-sa39 1000xxxxx 256 (4x64) kbytes sa38-sa35 0111xxxxx 256 (4x64) kbytes sa34-sa31 0110xxxxx 256 (4x64) kbytes sa30-sa27 0101xxxxx 256 (4x64) kbytes sa26-sa23 0100xxxxx 256 (4x64) kbytes sa22-sa19 0011xxxxx 256 (4x64) kbytes sa18-sa15 0010xxxxx 256 (4x64) kbytes sa14-sa11 0001xxxxx 256 (4x64) kbytes sa10-sa8 000011xxx 000010xxx 000001xxx 192 (3x64) kbytes sa7 000000111 8 kbytes sa6 000000110 8 kbytes sa5 000000101 8 kbytes sa4 000000100 8 kbytes sa3 000000011 8 kbytes sa2 000000010 8 kbytes sa1 000000001 8 kbytes sa0 000000000 8 kbytes
december 16, 2011 s29jl032j_00_06 s29jl032j 25 data sheet 8.11 write protect (wp#) the write protect function provides a hardware method of protecting ce rtain boot sectors without using v id . this function is one of two provided by the wp#/acc pin. if the system asserts v il on the wp#/acc pin, the device disables program and erase functions in the two outermost 8 kbyte boot sect ors independently of whether those sectors were prot ected or unprotected using the method described in boot sector/sector block protection and unprotection on page 23 . the two outermost 8 kbyte boot se ctors are the two sectors containing the lowest addr esses in a bottom-boot- configured device, or the two se ctors containing the hi ghest addresses in a t op-boot-configured device. if the system asserts v ih on the wp#/acc pin, the device reverts to whether the two outermost 8k byte boot sectors were last set to be protecte d or unprotected. that is , sector protection or un protection for these two sectors depends on whether they were last protec ted or unprotected usi ng the method described in boot sector/sector block pr otection and unprotection on page 23 . note that the wp#/acc pin must not be left floating or unconnected; inco nsistent behavior of the device may result. 8.12 temporary sector unprotect note: for the following discussion, the term ?sector? appli es to both sectors and sector blocks. a sector block consists of two or more adjacent sectors that ar e protected or unprotected at the same time (see table 8.6 on page 23 and table 8.7 on page 24 ). this feature allows temporary unprot ection of previously protected se ctors to change data in-system. the temporary sector unprotect mode is activated by setting the reset# pin to v id . during this mode, formerly protected sectors can be programmed or erased by selecti ng the sector addresses. once v id is removed from the reset# pin, all the previously protected sectors are protected again. figure 8.1 shows the algorithm, and figure 17.12 on page 55 shows the timing diagrams, for this feature. if the wp #/acc pin is at v il , the two outermost boot sectors will remain protect ed during the temporary sector unprotect mode. figure 8.1 temporary sector un protect operation notes: 1. all protected sectors unprotected (if wp#/acc = v il , the outermost two boot sect ors will remain protected). 2. all previously protected sectors are protected once again. table 8.8 wp#/acc modes wp# input voltage device mode v il disables programming and erasing in the two outermost boot sectors v ih enables programming and erasing in the two outermost boot sectors, dependent on whether they were last protected or unprotected v hh enables accelerated programming (acc). see accelerated program operation on page 15. start perform erase or program operations reset# = v ih temporary sector unprotect completed (note 2) reset# = v id (note 1)
26 s29jl032j s29jl032j_00_06 december 16, 2011 data sheet figure 8.2 in-system sector protect/unprotect algorithms sector protect: write 60h to sector address with a6 = 0, a1 = 1, a0 = 0 set up sector address wait 150 s verify sector protect: write 40h to sector address with a6 = 0, a1 = 1, a0 = 0 read from sector address with a6 = 0, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 ms first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector unprotect mode no sector unprotect: write 60h to sector address with a6 = 1, a1 = 1, a0 = 0 set up first sector address wait 15 ms verify sector unprotect: write 40h to sector address with a6 = 1, a1 = 1, a0 = 0 read from sector address with a6 = 1, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 ms data = 00h? last sector verified? remove v id from reset# write reset command sector unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector unprotect mode no all sectors protected? yes protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address set up next sector address no yes no yes no no yes no sector protect algorithm sector unprotect algorithm first write cycle = 60h? protect another sector? reset plscnt = 1
december 16, 2011 s29jl032j_00_06 s29jl032j 27 data sheet 8.13 secured silicon region the secured silicon region feature provides a fl ash memory region that enables permanent part identification through an elec tronic serial number (esn). the secur ed silicon region is 256 bytes in length, and may shipped unprotected, allowing cu stomers to utilize that sector in any manner they choose, or may shipped locked at the fact ory (upon customer request). the secured silicon indicator bit data will be 82h if factory locked, 42h if customer locked, or 02h if neither. refer to table 8.5 on page 22 for more details. the system accesses the secured silicon through a command sequence (see enter secured silicon region/ exit secured silicon region command sequence on page 33 ). after the system has written the enter secured silicon region command sequence, it may read the secured silicon region by using the addresses normally occupied by the boot sectors. this mode of operation continues until th e system issues the exit secured silicon region comm and sequence, or until powe r is removed from the dev ice. on power-up, or following a hardware reset, the device reverts to se nding commands to the first 256 bytes of sector 0. note that the acc function an d unlock bypass modes are not available when the secured silicon region is enabled. 8.13.1 factory locked: secured silicon regi on programmed and protected at the factory in a factory locked device, the secured silicon regi on is protected when the de vice is shi pped from the factory. the secured silicon region cannot be modified in any way. t he device is preprogrammed with both a random number and a secure esn. the 8-word ran dom number is at addresses 000000h-000007h in word mode (or 000000h-00000fh in byte mode). the secure esn is programmed in the next 8 words at addresses 000008h-00000fh (or 000010h-00001fh in byte mode). the dev ice is available preprogrammed with one of the following: ? a random, secure esn only ? customer code through spansion programming services ? both a random, secure esn and customer code through spansion programming services contact an your local sales office for deta ils on using spansion programming services. 8.13.2 customer lockable: secured silicon region not programmed or protected at the factory if the security feature is not required, the secured silicon regi on can be treated as an additional flash memory space. the secured silicon region can be r ead any number of times, but can be programmed and locked only once. note that the accelerated programming (acc) and unlock bypass functions are not available when programming the secured silicon region. ? write the three-cycle enter secured silicon regi on command sequence, and then follow the insystem sector protect algorithm as shown in figure 8.2 on page 26 , except that reset# may be at either v ih or v id . this allows in-system protection of the secured sili con region without raising any device pin to a high voltage. note that this method is only appli cable to the secured silicon region. ? to verify the protect/unprotect stat us of the secured silicon region , follow the algorithm shown in figure 8.3 on page 28 . once the secured silicon region is locked and verified, the system must write the exit secured silicon region command sequence to return to reading and writi ng the remainder of the ar ray. the secured silicon region lock must be used with caution since, once lock ed, there is no procedure available for unlocking the secured silicon region area and none of the bits in the secured silicon region memory space can be modified in any way.
28 s29jl032j s29jl032j_00_06 december 16, 2011 data sheet figure 8.3 secured silicon region protect verify 8.14 hardware data protection the command sequence requirement of unlock cycles fo r programming or erasing pr ovides data protection against inadvertent writes (refer to table 10.1 on page 38 for command definitions). in addition, the following hardware data protection measures pr event accidental erasure or prog ramming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down trans itions, or from system noise. 8.14.1 low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this protects data during v cc power-up and power-down. the command register and all in ternal program/erase circ uits are disabled, and the device resets to the read mode. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to pr event unintentional writes when v cc is greater than v lko . 8.14.2 write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. 8.14.3 logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. 8.14.4 power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power-up. write 60h to a ny a ddre ss write 40h to s ec u re s ilicon region a ddre ss with a6 = 0, a1 = 1, a0 = 0 s ta rt re s et# = v ih or v id w a it 1 m s re a d from s ec u re s ilicon region a ddre ss with a6 = 0, a1 = 1, a0 = 0 if d a t a = 00h, s ec u re s ilicon region i s u nprotected. if d a t a = 01h, s ec u re s ilicon region i s protected. remove v ih or v id from re s et# s ec u red s ilicon region exit comm a nd s ec u re s ilicon region protect verify complete
december 16, 2011 s29jl032j_00_06 s29jl032j 29 data sheet 9. common flash memory interface (cfi) the common flash interface (cfi) specification out lines device and host system software interrogation handshake, which allows specific vendor-s pecified software algorithms to be used for entire families of devices. software support can then be device-i ndependent, jedec id-independent, and forward- and backward-compatible for the specif ied flash device families. flash vendors can st andardize thei r existing interfaces for long-t erm compatibility. this device enters the cfi query mode when the syst em writes the cfi query command, 98h, to address 55h in word mode (or address aah in byte mode), any time the device is ready to read array data. the system can read cfi information at the addresses given in table 9.1 . to terminate reading cfi data, the system must write the reset command. the cfi query mode is not accessible when the device is executing an embedded program or embedded erase algorithm. the system can also write the cf i query command when the device is in the autoselect mode via the command register only (high volta ge method does not apply). the devic e enters the cfi query mode, and the system can read cfi data at the addresses given in table 9.1 . the system must write the reset command to return to reading array data. for further information, please refer to the cfi specification and cfi publication 100 . contact your local sales office for copies of these documents. table 9.1 cfi query identif ication string addresses (word mode) addresses (byte mode) data description 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 26h 28h 0002h 0000h primary oem command set 15h 16h 2ah 2ch 0040h 0000h address for primary extended table 17h 18h 2eh 30h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 32h 34h 0000h 0000h address for alternate oem extended table (00h = none exists) table 9.2 system interface string addresses (word mode) addresses (byte mode) data description 1bh 36h 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 38h 0036h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 3ah 0000h v pp min. voltage (00h = no v pp pin present) 1eh 3ch 0000h v pp max. voltage (00h = no v pp pin present) 1fh 3eh 0003h typical timeout per single byte/word write 2 n s 20h 40h 0000h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 42h 0009h typical timeout per individual block erase 2 n ms 22h 44h 000fh typical timeout for full chip erase 2 n ms (00h = not supported) 23h 46h 0004h max. timeout for byte/word write 2 n times typical 24h 48h 0000h max. timeout for buffer write 2 n times typical 25h 4ah 0004h max. timeout per individual block erase 2 n times typical 26h 4ch 0000h max. timeout for full chip erase 2 n times typical (00h = not supported)
30 s29jl032j s29jl032j_00_06 december 16, 2011 data sheet table 9.3 device geometry definition addresses (word mode) addresses (byte mode) data description 27h 4eh 0016h device size = 2 n byte 28h 29h 50h 52h 0002h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 54h 56h 0000h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 58h 0002h number of erase block regions within device 2dh 2eh 2fh 30h 5ah 5ch 5eh 60h 0007h 0000h 0020h 0000h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 32h 33h 34h 62h 64h 66h 68h 003eh 0000h 0000h 0001h erase block region 2 information (refer to the cfi specification or cfi publication 100) 35h 36h 37h 38h 6ah 6ch 6eh 70h 0000h 0000h 0000h 0000h erase block region 3 information (refer to the cfi specification or cfi publication 100) 39h 3ah 3bh 3ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h erase block region 4 information (refer to the cfi specification or cfi publication 100)
december 16, 2011 s29jl032j_00_06 s29jl032j 31 data sheet table 9.4 primary vendor-specific extended query addresses (word mode) addresses (byte mode) data description 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 86h 0031h major version number, ascii (reflects modifications to the silicon) 44h 88h 0033h minor version number, ascii (reflects modifications to the cfi table) 45h 8ah 000ch address sensitive unlock (bits 1-0) 0 = required, 1 = not required process technology (bits 7-2) 0011 = 0.11 m floating gate 46h 8ch 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 8eh 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 90h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 92h 0004h sector protect/unprotect scheme 01 = 29f040 mode, 02 = 29f016 mode, 03 = 29f400, 04 = 29lv800 mode 4ah 94h 00xxh number of sectors (excluding bank 1) xx = 38 (models 01, 02, 21, 22) xx = 30 (models 31, 32) xx = 20 (models 41, 42) 4bh 96h 0000h burst mode type 00 = not supported, 01 = supported 4ch 98h 0000h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 9ah 0085h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 9ch 0095h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 9eh 000xh top/bottom boot sector flag 02h = bottom boot device, 03h = top boot device 50h a0h 0000h program suspend 0 = not supported, 1 = supported 57h aeh 000xh bank organization 00 = data at 4ah is zero x = 4 (4 banks, models 01, 02) x = 2 (2 banks, all other models) 58h b0h 00xxh bank 1 region information - number of sectors on bank 1 xx = 0f (models 01, 02, 21, 22) xx = 17 (models 31, 32) xx = 27 (models 41, 42) 59h b2h 00xxh bank 2 region information - number of sectors in bank 2 xx = 18 (models 01, 02) xx = 38 (models 21, 22) xx = 30 (models 31, 32) xx = 20 (models 41, 42) 5ah b4h 00xxh bank 3 region information - number of sectors in bank 3 xx = 18 (models 01, 02) xx = 00 (all other models) 5bh b6h 00xxh bank 4 region information - number of sectors in bank 4 xx = 08 (models 01, 02) xx = 00 (all other models)
32 s29jl032j s29jl032j_00_06 december 16, 2011 data sheet 10. command definitions writing specific address and data sequences into the command register initiates device operations. table 10.1 on page 38 defines the valid register command sequences. writing incorrect address and data values or writing t hem in the improper sequence may place the de vice in an unknown state. a hardware reset may be required to return the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to ac characteristics on page 48 for timing diagrams. 10.1 reading array data the device is automatically set to reading array data after device power -up. no commands are required to retrieve data. each bank is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command , the corresponding bank enters the erase-suspend- read mode, after which the system can read data fr om any non-erase-suspended sector within the same bank. the system can read array data using the standard read ti ming, except that if it reads at an address within erase-suspended sectors, t he device outputs status dat a. after completing a programming operation in the erase suspend mode, the system may once again read array data with t he same exception. see erase suspend/erase resume commands on page 37 for more information. the system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if dq5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. see reset command on page 32 , for more information. see also requirements for reading array data on page 15 for more information. read-only operations on page 48 provides the r ead parameters, and figure 17.1 on page 48 shows the timing diagram. 10.2 reset command writing the reset command resets the banks to the read or erase-suspend-read mode. the reset command may be written between the se quence cycles in an erase command sequence before erasing begins. this resets the bank to which the syst em was writing to the read mode. once erasure begins, however, the device ignores reset comma nds until the operation is complete. the reset command may be written between the seq uence cycles in a program command sequence before programming begins. this resets the bank to which the system was writing to the read mode. if the program command sequence is written to a bank that is in the erase suspend mode, writing the reset command returns that bank to the erase- suspend-read mode. once programmi ng begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the se quence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to the read mode. if a bank entered the autoselect mode while in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. if dq5 goes high during a program or erase operation, writi ng the reset command returns the bank to the read mode (or erase-suspend-read mode if that bank was in erase suspe nd). please note t hat the ry/by# signal remains low until this reset is issued.
december 16, 2011 s29jl032j_00_06 s29jl032j 33 data sheet 10.3 autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sect or is protected. the autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. the autoselect command may not be written while the device is active ly programming or erasing in another bank. the autoselect command sequence is init iated by first writing two unlock cy cles. this is followed by a third write cycle that cont ains the bank address and the autoselect comm and. the bank then enters the autoselect mode. the system may read any number of autoselec t codes without reinitiating the command sequence. table 10.1 on page 38 shows the address and data requirement s. to determine sector protection information, the system must wr ite to the appropriate bank address (ba) and sector address (sa). table 8.3 on page 18 and table 8.4 on page 20 show the address range and bank number associated with each sector. the system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in erase suspend). 10.4 enter secured silicon region/exi t secured silicon region command sequence the system can access t he secured silicon region region by issuin g the three-cycle enter secured silicon region command sequence. the device continues to a ccess the secured silicon region until the system issues the four-cycle ex it secured silico n region command s equence. the exit secured silicon region command sequence returns t he device to normal o peration. the secured silicon region is not accessible when the device is executing an embedded program or embedded erase algorithm. table 10.1 on page 38 shows the address and data requirements for both command sequences. see also secured silicon region on page 27 for further information. note that the acc function and unlock bypass modes are not available when the secured silicon region is enabled. 10.5 byte/word program command sequence the system may program the device by word or byte , depending on the state of the byte# pin. programming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write cycles, followed by the program set-up co mmand. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide furt her controls or timings. the device automatically provides internally generat ed program pulses and verifies the programmed cell margin. table 10.1 on page 38 shows the address and dat a requirements for the byte program command sequence. when the embedded program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. the system c an determine the status of the program operation by using dq7, dq6, or ry/by#. refer to write operation status on page 39 for information on these status bits. any commands written to the device during the embedded program al gorithm are ignored. note that a hardware reset immediately terminates the program operation. the program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. note that the secured silicon region, autoselect, and cfi functions are u navailable when a program operation is in progress. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from ?0? back to a ?1.? attempting to do so may cause that bank to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was successful. howe ver, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.?
34 s29jl032j s29jl032j_00_06 december 16, 2011 data sheet 10.5.1 unlock bypass command sequence the unlock bypass feature allows the system to progra m bytes or words to a bank faster than using the standard program command sequence. the unlock bypass co mmand sequence is initiated by first writing two unlock cycles. this is followed by a third write cycl e containing the unlock bypass command, 20h. that bank then enters the unlock bypass mode. a two-cycle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initia l two unlock cycles requir ed in the standard program command sequence, resulting in faster total programming time. table 10.1 on page 38 shows the requirements for the command sequence. during the unlock bypass mode, only the unlock by pass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system mu st issue the two-cycle unl ock bypass reset command sequence. ( table 10.1 on page 38 ). the device offers accelerated program operations th rough the wp#/acc pin. when the system asserts v hh on the wp#/acc pin, the device automatically enters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequence. the device uses the higher voltage on the wp#/ acc pin to accelerate the operation. note that the wp#/acc pin must not be at v hh for any operation other than accelerated programming, or devic e damage may result. in addition, the wp#/acc pin must not be left floating or unconnected; inconsiste nt behavior of the device may result. figure 10.1 illustrates the algorithm for the program operation. refer to erase and program operations on page 51 for parameters, and figure 17.5 on page 52 for timing diagrams. figure 10.1 program operation note: see table 10.1 on page 38 for program command sequence. start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress
december 16, 2011 s29jl032j_00_06 s29jl032j 35 data sheet 10.6 chip erase command sequence chip erase is a six bus cycle operation. the chip er ase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlo ck write cycles are then fo llowed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedd ed erase algorithm automatically pr eprograms and verifies the entire memory for an all zero data pattern prior to electrical er ase. the system is not required to provide any controls or timings during these operations. table 10.1 on page 38 shows the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. the system can determine the status of the erase operation by us ing dq7, dq6, dq2, or ry/ by#. refer to write operation status on page 39 for information on these status bits. any commands written during t he chip erase operation are ig nored. however, note that a hardware reset immediately terminates the erase op eration. if that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to en sure data integrity. note that the secured silicon region, autoselect, and cfi functions are unav ailable when an erase operation is in progress. figure 10.2 on page 36 illustrates the algorithm for the erase operation. refer to erase and program operations on page 51 for parameters, and figure 17.7 on page 53 for timing diagrams. 10.7 sector erase command sequence sector erase is a six bus cycle ope ration. the sector erase command s equence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sect or erase command. table 10.1 on page 38 shows the address and data requirements for t he sector erase command sequence. the device does not require the system to preprogram prio r to erase. the embedded erase algorithm automatically programs and verifies the entire sector for an all zero data patt ern prior to electrical erase. the system is not required to provide any cont rols or timings during these operations. after the command sequence is written, a sector erase ti me-out of 50 s occurs. du ring the time- out period, additional sector addr esses and sector erase commands may be writ ten. however, these additional erase commands are only one bus cycle long and should be i dentical to the sixth cycle of the standard erase command explained above. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise erasure may begin. any sector er ase address and command following the exceeded time- out may or may not be accepted. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. if any command other than 30h, b0h, f0h is input during the time-out period, the normal operation will not be guaranteed. the system must rewrite the co mmand sequence and any additional addresses and commands. the system can monitor dq3 to determine if the se ctor erase timer has timed out (see dq3: sector erase timer on page 43 .). the time-out begins from the rising edge of t he final we# or ce# pulse (first rising edge) in the command sequence. when the embedded erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. note that while the embedded erase operati on is in progress, the system can read data from the non-erasing bank. the system can determine the status of the erase operation by reading dq7, dq6, dq2, or ry/by# in the erasing bank. refer to write operation status on page 39 for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a hardware reset immediately terminates the erase operat ion. if that occurs, the sector erase command sequence should be reinitiat ed once that bank has retur ned to reading array data, to ensure data integrity. note that the secured silico n region, autoselect, and cfi functions are unavailable when an erase operation is in progress. figure 10.2 on page 36 illustrates the algorithm for the erase operation. refer to erase and program operations on page 51 for parameters, and figure 17.7 on page 53 for timing diagrams.
36 s29jl032j s29jl032j_00_06 december 16, 2011 data sheet figure 10.2 erase operation notes: 1. see table 10.1 on page 38 for erase command sequence. 2. see dq3: sector erase timer on page 43 for information on the sector erase timer. start write erase command sequence (notes 1, 2) data poll to erasing bank from system data = ffh? no yes erasure completed embedded erase algorithm in progress
december 16, 2011 s29jl032j_00_06 s29jl032j 37 data sheet 10.8 erase suspend/er ase resume commands the erase suspend command, b0h, allows the system to interrupt a sector eras e operation and then read data from, or program data to, any se ctor not selected for erasure. t he bank address is r equired when writing this command. this command is valid only during the se ctor erase operation, incl uding the 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorith m. the bank address must contain one of the sectors currently selected for erase. when the erase suspend command is written during the sector erase operation, the device requires a maximum of 35 s to suspend the erase operation. however, when t he erase suspend command is written during the sector erase time-out, th e device immediately terminates t he time-out period and suspends the erase operation. after the erase operation has been suspended, the bank enters the erase-suspend-read mode. the system can read data from or program data to any sector not selected fo r erasure. (the device ?erase suspends? all sectors selected for erasure.) it is not recommended to program the secured silicon region after an erase suspend, as proper device functionality cannot be guaranteed. reading at any address within erase- suspended sectors produces status in formation on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a se ctor is actively erasing or is erase-suspended. refer to write operation status on page 39 for information on these status bits. after an erase-suspended program oper ation is complete, the bank returns to the erase-suspend-read mode. the system can determine the status of the program operation using the dq7 or dq 6 status bits, just as in the standard byte progr am operation. refer to write operation status on page 39 for more information. in the erase-suspend-read mode, the system can also issue the autose lect command sequence. the device allows reading autoselect codes even at addresses within erasing sectors, since t he codes are not stored in the memory array. when the devic e exits the autoselect mode, the dev ice reverts to the erase suspend mode, and is ready for another valid operation. refer to autoselect mode on page 22 and autoselect command sequence on page 33 for details. to resume the sector erase oper ation, the system must write t he erase resume command. the bank address of the erase-suspended bank is required when writing this command. further writes of the resume command are ignored. another erase suspend command c an be written after the ch ip has resumed erasing.
38 s29jl032j s29jl032j_00_06 december 16, 2011 data sheet legend: x = don?t care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever ha ppens later. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect m ode) or erased. address bits a2 0?a12 uniquely select any sector. refer to table 8.3 on page 18 and table 8.4 on page 20 for information on sector addresses. ba = address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased. a20?a18 uniquely sel ect a bank. notes: 1. see table 8.1 on page 14 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle and the fourth, fifth, and sixth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. data bits dq15?dq8 are don?t care in command sequences, except for rd and pd. 5. unless otherwise noted, address bits a20?a11 are don?t cares for unlock and command cycles, unless sa or pa is required. 6. no unlock or command cycles required when bank is reading array data. 7. the reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in erase suspend) w hen a bank is in the autoselect mode, or if dq5 goes high (while the bank is providing status information). 8. the fourth cycle of the autoselect command sequence is a read cycle. the system must provide the bank address to obtain the m anufacturer id, device id, or secured silicon region factory protect info rmation. data bits dq15?dq8 are don?t ca re. while reading the autoselect addresses, the bank address must be the same until a reset command is given. see autoselect command sequence on page 33 for more information. 9. for models 01, 02, the device id must be read across the fourth, fifth, and sixth cycles. 10. the data is 82h for factory locked, 42h for customer locked, and 02h for not factory/customer locked. table 10.1 s29jl032j command definitions command sequence (note 1) cycles bus cycles (notes 2 ? 5 ) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 6) 1ra rd reset (note 7) 1xxx f0 autoselect (note 8) manufacturer id word 4 555 aa 2aa 55 (ba)555 90 (ba)x00 01 byte aaa 555 (ba)aaa device id (note 9) word 6 555 aa 2aa 55 (ba)555 90 (ba)x01 see table 8.5 (ba)x0e see table 8.5 (ba)x0f see table 8.5 byte aaa 555 (ba)aaa (ba)x02 (ba)x1c (ba)x1e secured silicon region factory protect (note 10) word 4 555 aa 2aa 55 (ba)555 90 (ba)x03 82/02 byte aaa 555 (ba)aaa (ba)x06 boot sector/sector block protect verify (note 11) word 4 555 aa 2aa 55 (ba)555 90 (sa)x02 00/01 byte aaa 555 (ba)aaa (sa)x04 enter secured silicon region word 3 555 aa 2aa 55 555 88 byte aaa 555 aaa exit secured silicon region word 4 555 aa 2aa 55 555 90 xxx 00 byte aaa 555 aaa program word 4 555 aa 2aa 55 555 a0 pa pd byte aaa 555 aaa unlock bypass word 3 555 aa 2aa 55 555 20 byte aaa 555 aaa unlock bypass program (note 12) 2 xxx a0 pa pd unlock bypass reset (note 13) 2 xxx 90 xxx 00 chip erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 byte aaa 555 aaa aaa 555 aaa sector erase (note 17) word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 byte aaa 555 aaa aaa 555 erase suspend (note 14) 1ba b0 erase resume (note 15) 1ba 30 cfi query (note 16) word 1 55 98 byte aa
december 16, 2011 s29jl032j_00_06 s29jl032j 39 data sheet 11. the data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. 12. the unlock bypass command is required prior to the unlock bypass program command. 13. the unlock bypass reset command is required to return to the read mode when the bank is in the unlock bypass mode. 14. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the er ase suspend command is valid only during a sector erase operation, and requires the bank address. 15. the erase resume command is valid only during the erase suspend mode, and requires the bank address. 16. command is valid when device is ready to read array data or when device is in autoselect mode. 17. additional sector erase commands during the time-out period after an initial sector erase are one cycle long and identical t o the sixth cycle of the sector erase command sequence (sa / 30). 11. write operation status the device provides several bits to determine the status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. table 11.1 on page 43 and the following subsections describ e the function of these bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. the device also provides a hardware-based output signal, ry/by#, to determine whether an embedded program or erase operation is in progress or has been completed. 11.1 dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded prog ram or erase algorithm is in progress or completed, or w hether a bank is in erase suspend. da ta# polling is valid after the rising edge of the final we# pulse in the command sequence. during the embedded program algorithm, the devic e outputs on dq7 the complement of the datum programmed to dq7. this dq7 status also appl ies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programm ed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for approximately 1 s, then that bank returns to the read mode. during the embedded erase algorithm, data# polli ng produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the bank enters the er ase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of th e sectors selected for erasur e to read valid status information on dq7. after an erase command sequence is written, if all sect ors selected for erasing are protected, data# polling on dq7 is active for approximately 3 ms, then the bank returns to the read mode. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. however, if the system reads dq7 at an address within a pr otected sector, the status may not be valid. when the system detects dq7 has changed from the co mplement to true data, it can read valid data at dq15?dq0 (or dq7?dq0 for x8-only device) on the following read cycles. just prior to the completion of an embedded program or erase operation, dq7 may chan ge asynchronously with dq15?dq8 (dq7?dq0 for x8-only device) while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system sa mples the dq7 output, it may read the status or valid data. even if the device has comple ted the program or erase operation and dq7 has valid data, the data output s on dq15?dq0 may be still invalid. valid da ta on dq15?dq0 (or dq7?dq0 for x8-only device) will appear on successive read cycles. table 11.1 on page 43 shows the outputs for data# polling on dq7. figure 11.1 on page 40 shows the data# polling algorithm. figure 17.9 on page 54 shows the data# polling timing diagram.
40 s29jl032j s29jl032j_00_06 december 16, 2011 data sheet figure 11.1 data# polling algorithm notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5. 11.2 ry/by#: ready/busy# the ry/by# is a dedicated, open- drain output pin which indicates whether an embedded algorithm is in progress or complete. the ry/by# stat us is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-dr ain output, several ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the device is actively erasing or programming. (thi s includes programming in the erase suspend mode.) if the output is high (ready), the device is in the read mode, th e standby mode, or one of the banks is in t he erase-suspend-read mode. table 11.1 on page 43 shows the outputs for ry/by#. when dq5 is set to ?1?, ry/by# wi ll be in the busy state, or ?0?. 11.3 dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded progra m or erase algorithm is in progress or complete, or whether the device has entered the erase suspend m ode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and duri ng the sector erase time-out. $1??$ata 9e s .o .o $1?? .o 9e s 9e s &!), 0!33 2ead?$1n$1 !ddr??6! 2ead?$1n$1 !ddr??6! $1??$ata 34!24
december 16, 2011 s29jl032j_00_06 s29jl032j 41 data sheet during an embedded program or eras e algorithm operation, successive read cycles to any address cause dq6 to toggle. the system may use either oe# or ce # to control the read cycles. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sector s selected for erasing are protected, dq6 toggles for approximately 3 ms, then returns to reading array data. if not all sele cted sectors are protected, the embedded erase algorithm erases t he unprotected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 toget her to determine whether a sector is actively erasing or is erase- suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode , dq6 stops toggling. howe ver, the system must also use dq2 to determine which se ctors are erasing or erase-suspended. alternatively, the system can use dq7 (see dq7: data# polling on page 39 ). if a program address falls within a protected sector, dq6 to ggles for approximately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during th e erase-suspend-program mode, and st ops toggling once the embedded program algorithm is complete. figure 11.2 toggle bit algorithm note: the system should recheck the toggle bit even if dq5 = ?1? becaus e the toggle bit may stop toggling as dq5 changes to ?1.? see the subsections on dq6 and dq2 for more information. start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete toggle bit = toggle? read byte twice (dq7Cdq0) address = va read byte (dq7Cdq0) address =va read byte (dq7Cdq0) address =va
42 s29jl032j s29jl032j_00_06 december 16, 2011 data sheet 11.4 dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whet her that sector is erase- suspended. toggle bit ii is valid after the rising edge of the fi nal we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either oe# or ce # to control the read cycles.) bu t dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq 6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot di stinguish which sectors are selected for erasure. thus, both status bits are required for sect or and mode inform ation. refer to table 11.1 on page 43 to compare outputs for dq2 and dq6. figure 11.2 on page 41 shows the toggle bit algorit hm in flowchart form, and dq2: toggle bit ii on page 42 explains the algorithm. see also dq6: toggle bit i on page 40 . figure 17.10 on page 54 shows the toggle bit timing diagram. figure 17.11 on page 55 shows the differences between dq2 and dq6 in graphical form. 11.5 reading toggle bits dq6/dq2 refer to figure 11.2 on page 41 for the following discussion. whenever the system initially begins reading toggle bit status, it must read dq15?dq0 (or dq7?dq0 for x8-only device) at least twice in a row to determine whether a toggle bi t is toggling. typica lly, the system would note and store the value of the toggle bit after the first read. a fter the second read, the system would compar e the new value of the toggle bit with the first. if the toggle bit is not to ggling, the device has completed the pr ogram or erase operation. the system can read array data on dq15?dq0 (or dq7?dq0 for x8-only device) on the following read cycle. however, if after the initial two read cycles, the sy stem determines t hat the toggle bit is still toggling, the system also should note whether the va lue of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bi t is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has succ essfully completed the program or erase operation. if it is still toggling, the device di d not completed the operati on successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially det ermines that the t oggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 th rough successive read cycles, determining the status as described in the previous par agraph. alternatively, it may choose to perform other system tasks. in this case, the sy stem must start at the beginning of the algorithm when it returns to determine the status of the operati on (top of figure 11.2 on page 41 ). 11.6 dq5: exceede d timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not successfully completed. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously programmed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the timing lim it has been exceeded, dq5 produces a ?1.? the rdy/bsy# pin will be in the bu sy state under th is condition. under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode).
december 16, 2011 s29jl032j_00_06 s29jl032j 43 data sheet 11.7 dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not erasure has begun. (the sect or erase timer does not apply to the ch ip erase command.) if additional sectors are selected for erasure, t he entire time-out also applies after each additional sector erase command. when the time-out period is complete, dq3 sw itches from a ?0? to a ?1.? if the time between additional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor dq3. see also sector erase command sequence on page 35 . after the sector erase command is wr itten, the sys tem should read the st atus of dq7 (dat a# polling) or dq6 (toggle bit i) to ensure t hat the device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all further commands (e xcept erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the device will acce pt additional sector erase commands. to ensure the command has been acc epted, the system softwa re should check the status of dq3 prior to and following each subsequent sector erase command. if dq 3 is high on the second status check, the last command might not have been accepted. table 11.1 shows the status of dq3 relati ve to the other status bits. notes: 1. dq5 switches to ?1? when an embedded program or embedded erase operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. when reading write operation status bits, the system must always provide the bank address where the embedded algorithm is in progress. the device outputs array data if the system addresses a non-busy bank. table 11.1 write operation status status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm in busy erasing sector 0 toggle 0 1 toggle 0 in not busy erasing sector 0 toggle 0 1 no toggle 0 erase suspend mode erase-suspend- read erase suspended sector 1 no toggle 0 n/a toggle 1 non-erase suspended sector data data data data data 1 erase-suspend-program dq7# toggle 0 n/a n/a 0
44 s29jl032j s29jl032j_00_06 december 16, 2011 data sheet 12. absolute maximum ratings notes: 1. minimum dc voltage on input or i/o pins is ?0.5v. during voltage transitions, input or i/o pins may overshoot v ss to ?2.0v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5v. see figure 12.1 on page 44 . during voltage transitions, input or i/o pins may overshoot to v cc +2.0v for periods up to 20 ns. see figure 12.2 on page 44 . 2. minimum dc input voltage on pins a9, oe#, reset#, and wp#/acc is ?0.5v. during voltage transitions, a9, oe#, wp#/acc, and reset# may overshoot v ss to ?2.0v for periods of up to 20 ns. see figure 12.1 on page 44 . maximum dc input voltage on pin a9 is +12.5v which may overshoot to +14.0v for periods up to 20 ns. maximum dc input voltage on wp#/acc is +9.5v which may overshoot to +12.0v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one seco nd. 4. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress ratin g only; functional operation of the device at these or any other conditi ons above those indicated in the operational sections of this d ata sheet is not implied. exposure of the device to absolute maximum rating conditi ons for extended periods may affect device reliability. figure 12.1 maximum negative overshoot waveform figure 12.2 maximum positive overshoot waveform storage temperature, plastic packages ?65c to +150c ambient temperature with power applied ?65c to +125c voltage with respect to ground, v cc (note 1) ?0.5v to +4.0v a9 and reset# (note 2) ?0.5v to +12.5v wp#/acc ?0.5v to +9.5v all other pins (note 1) ?0.5v to v cc +0.5v output short circuit current (note 3) 200 ma 20 ns 20 ns +0.8v ?0.5v 20 ns ?2.0v 20 ns 20 ns v cc +2.0v v cc +0.5v 20 ns 2.0v
december 16, 2011 s29jl032j_00_06 s29jl032j 45 data sheet 13. operating ranges industrial (i) devices ambient temperature (t a ) ?40c to +85c v cc supply voltages v cc for standard voltage range 2.7v to 3.6v operating ranges define those limits between which the func tionality of the device is guaranteed. 14. dc characteristics 14.1 cmos compatible notes: 1. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . 2. maximum i cc specifications are tested with v cc = v cc max. 3. i cc active while embedded erase or embedded program is in progress. 4. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. typical sleep mode current is 200 na. 5. not 100% tested. parameter symbol parameter description test conditions min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9 and reset# input load current v cc = v cc max , oe# = v ih ; a9 or reset# = 12.5v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max , oe# = v ih 1.0 a i lr reset leakage current v cc = v cc max ; reset# = 12.5v 35 a i cc1 v cc active read current (notes 1 , 2 ) ce# = v il , oe# = v ih , byte mode 5mhz 10 16 ma 1mhz 2 4 ce# = v il , oe# = v ih , word mode 5mhz 10 16 1mhz 2 4 i cc2 v cc active write current (notes 2 , 3 )ce# = v il , oe# = v ih , we# = v il 15 30 ma i cc3 v cc standby current (note 2) ce#, reset# = v cc 0.3v 0.2 5 a i cc4 v cc reset current (note 2) reset# = v ss 0.3v 0.2 5 a i cc5 automatic sleep mode (notes 2 , 4 ) v ih = v cc 0.3v; v il = v ss 0.3v 0.2 5 a i cc6 v cc active read-while-program current (note 2) ce# = v il , oe# = v ih , 1mhz byte 21 45 ma word 21 45 i cc7 v cc active read-while-erase current (note 2) ce# = v il , oe# = v ih , 1mhz byte 21 45 ma word 21 45 i cc8 v cc active program-while-erase-suspended current (notes 2 , 5 ) ce# = v il , oe# = v ih 17 35 ma v il input low voltage ?0.5 0.8 v v ih input high voltage 0.7 x v cc v cc + 0.3 v v hh voltage for wp#/acc sector protect/ unprotect and program acceleration v cc = 3.0v 10% 8.5 9.5 v v id voltage for autoselect and temporary sector unprotect v cc = 3.0v 10% 8.5 12.5 v v ol output low voltage i ol = 2.0 ma, v cc = v cc min 0.45 v v oh1 output high voltage i oh = ?2.0 ma, v cc = v cc min 0.85 x v cc v v oh2 i oh = ?100 a, v cc = v cc min v cc ?0.4 v lko low v cc lock-out voltage (note 5) 1.8 2.0 2.5 v
46 s29jl032j s29jl032j_00_06 december 16, 2011 data sheet 14.2 zero-power flash figure 14.1 i cc1 current vs. time (showing ac tive and automatic sleep currents) note: addresses are switching at 1 mhz figure 14.2 typical i cc1 vs. frequency note: t = 25c 25 20 15 10 5 0 0 500 1000 1500 2000 2500 3000 3500 4000 supply current in ma time in ns 10 8 2 0 1 2345 frequency in mhz supply current in ma 2.7v 3.6v 4 6 12
december 16, 2011 s29jl032j_00_06 s29jl032j 47 data sheet 15. test conditions figure 15.1 test setup note: diodes are in3064 or equivalent. note: 1. input rise and fall times are 0-100%. 16. key to switching waveforms figure 16.1 input waveforms and measurement levels table 15.1 test specifications test condition 60 70 unit output load capacitance, c l 30 100 pf input rise and fall times (1) 5ns input pulse levels 0.0 or vcc v input timing measurement reference levels 0.5 vcc v output timing measurement reference levels 0.5 vcc v c l device under te s t waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high-z) vcc 0.0 v 0.5 vcc 0.5 vcc output measurement level input
48 s29jl032j s29jl032j_00_06 december 16, 2011 data sheet 17. ac characteristics 17.1 read-only operations notes: 1. not 100% tested. 2. see figure 15.1 on page 47 and table 15.1 on page 47 for test specifications 3. measurements performed by placing a 50 ohm termination on the data pin with a bias of v cc /2. the time from oe# high to the data bus driven to v cc /2 is taken as t df. figure 17.1 read operation timings parameter description test setup speed options jedec std. 60 70 unit t avav t rc read cycle time (note 1) min 60 70 ns t avqv t acc address to output delay ce#, oe# = v il max 60 70 ns t elqv t ce chip enable to output delay oe# = v il max 60 70 ns t glqv t oe output enable to output delay max 25 30 ns t ehqz t df chip enable to output high-z (notes 1 , 3 ) max 16 ns t ghqz t df output enable to output high-z (notes 1 , 3 ) max 16 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 5 10 ns t oh t ce o u tp u t s we# addre ss e s ce# oe# high-z o u tp u t v a lid high-z addre ss e s s t ab le t rc t acc t oeh t rh t oe t rh 0 v ry/by# re s et# t df
december 16, 2011 s29jl032j_00_06 s29jl032j 49 data sheet 17.2 hardware reset (reset#) note: not 100% tested. figure 17.2 reset timings parameter description all speed options unit jedec std t ready reset# pin low (during embedded algorithms) to read mode (see note) max 35 s t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 50 ns t rpd reset# low to standby mode min 35 s t rb ry/by# recovery time min 0 ns reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb
50 s29jl032j s29jl032j_00_06 december 16, 2011 data sheet 17.3 word/byte configuration (byte#) figure 17.3 byte# timings for read operations figure 17.4 byte# timings for write operations note: refer to the table in erase and program operations on page 51 for t as and t ah specifications. parameter speed options jedec std. description 60 70 unit t elfl/ t elfh ce# to byte# switching low or high max 5 ns t flqz byte# switching low to output high-z max 16 ns t fhqv byte# switching high to output active max 60 70 ns dq15 output data output (dq7?dq0) ce# oe# byte# t elfl dq14?dq0 data output (dq14?dq0) dq15/a-1 address input t flqz byte# switching from word to byte mode dq15 output data output (dq7?dq0) byte# t elfh dq14?dq0 data output (dq14?dq0) dq15/a-1 address input t fhqv byte# switching from byte to word mode ce# we# byte# the falling edge of the last we# signal t hold (t ah ) t set (t as )
december 16, 2011 s29jl032j_00_06 s29jl032j 51 data sheet 17.4 erase and program operations notes: 1. not 100% tested. 2. see erase and programming performance on page 58 for more information. parameter description speed options jedec std 60 70 unit t avav t wc write cycle time (note 1) min 60 70 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 12 ns t wlax t ah address hold time min 35 35 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 35 40 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 25 30 ns t whdl t wph write pulse width high min 25 30 ns t sr/w latency between read and write operations min 0 ns t whwh1 t whwh1 programming operation (note 2) byte typ 6 s word typ 6 t whwh1 t whwh1 accelerated programming operation, byte or word (note 2) ty p 4 s t whwh2 t whwh2 sector erase operation (note 2) ty p 0 . 5 s e c t vcs v cc setup time (note 1) min 50 s t rb write recovery time from ry/by# min 0 ns t busy program/erase valid to ry/by# delay max 90 ns t esl erase suspend latency max 35 s
52 s29jl032j s29jl032j_00_06 december 16, 2011 data sheet figure 17.5 program operation timings notes: 1. pa = program address, pd = program data, d out is the true data at the program address. 2. illustration shows device in word mode. figure 17.6 accelerated program timing diagram oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa wp#/acc t vhh v hh v il or v ih v il or v ih t vhh
december 16, 2011 s29jl032j_00_06 s29jl032j 53 data sheet figure 17.7 chip/sector erase operation timings notes: 1. sa = sector address (for sector erase), va = valid address for reading status data (see write operation status on page 39 ). 2. these waveforms are for the word mode. figure 17.8 back-to-back read/wr ite cycle timings oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy oe# ce# we# addresses t oh data valid in valid in valid pa valid ra t wc t wph t ah t wp t ds t dh t rc t ce valid out t oe t acc t oeh t ghwl t df valid in ce# or ce2# controlled write cycles we# controlled write cycle valid pa valid pa t cp t cph t wc t wc read cycle t sr/w
54 s29jl032j s29jl032j_00_06 december 16, 2011 data sheet figure 17.9 data# polling timings (d uring embedded algorithms) note: va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read c ycle. figure 17.10 toggle bit timings (during embedded algorithms) note: va = valid address; not required for dq6. illustration shows first two status cycle after command sequence, last status read cy cle, and array data read cycle. we# ce# oe high-z t oe high-z dq7 dq0?dq6 ry/by# t busy compleme tru addresses va t oeh t ce t ch t oh t df va va status complement status tru valid data valid data t acc t rc oe# ce# we# addre ss e s t oeh t dh t aht t a s o t oeph t oe v a lid d a t a (fir s t re a d) ( s econd re a d) ( s top s toggling) t cph t aht t a s dq6/dq2 v a lid d a t a v a lid s t a t us v a lid s t a t us v a lid s t a t us ry/by#
december 16, 2011 s29jl032j_00_06 s29jl032j 55 data sheet figure 17.11 dq2 vs. dq6 note: dq2 toggles only when read at an address within an erase-suspended sector. the system may use oe# or ce# to toggle dq2 and dq6. 17.5 temporary sector unprotect note: not 100% tested. figure 17.12 temporary sector unpr otect timing diagram enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing parameter description all speed options jedec std unit t vidr v id rise and fall time (see note) min 500 ns t vhh v hh rise and fall time (see note) min 250 ns t rsp reset# setup time for temporary sector unprotect min 4 s t rrb reset# hold time from ry/by# high for temporary sector unprotect min 4 s reset# t vidr v id v ss , v il , or v ih v id v ss , v il , or v ih ce# we# ry/by# t vidr t rsp program or erase command sequence t rrb
56 s29jl032j s29jl032j_00_06 december 16, 2011 data sheet figure 17.13 sector/sector block protec t and unprotect timing diagram note: *for sector protect, a6 = 0, a1 = 1, a0 = 0. for sector unprotect, a6 = 1, a1 = 1, a0 = 0 17.6 alternate ce# controlled erase and program operations notes: 1. not 100% tested. 2. see erase and programming performance on page 58 for more information. sector group protect: 150 s sector group unprot ect: 15 ms 1 s reset# sa, a6, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector group protect/unprotect verify v id v ih parameter speed options jedec std. description 60 70 unit t avav t wc write cycle time (note 1) min 60 70 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 35 35 ns t dveh t ds data setup time min 30 30 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 25 35 ns t ehel t cph ce# pulse width high min 25 30 ns t whwh1 t whwh1 programming operation (note 2) byte typ 6 s word typ 6 t whwh1 t whwh1 accelerated programming operation, byte or word (note 2) ty p 4 s t whwh2 t whwh2 sector erase operation (note 2) ty p 0 . 5 s e c
december 16, 2011 s29jl032j_00_06 s29jl032j 57 data sheet figure 17.14 alternate ce# controlled write (erase/program) operation timings notes: 1. figure indicates last two bus cycles of a program or erase operation. 2. pa = program address, sa = sector address, pd = program data. 3. dq7# is the complement of the data written to the device. d out is the data written to the device. 4. waveforms are for the word mode. t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy
58 s29jl032j s29jl032j_00_06 december 16, 2011 data sheet 18. erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25c, v cc = 3.0v, 100,000 cycles; checkerboard data pattern. 2. under worst case conditions of 90c, v cc = 2.7v, 1,000,000 cycles. 3. in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 4. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 10.1 on page 38 for further information on command definitions. 5. the device has a minimum program and erase cycle endurance of 100,000 cycles per sector. 19. pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. parameter typ (note 1) max (note 2) unit comments sector erase time 0.5 5 sec excludes 00h programming prior to erasure (note 3) chip erase time 39 sec byte program time 6 80 s excludes system level overhead (note 4) word program time 6 80 s accelerated byte/word program time 4 70 s parameter symbol parameter description test setup max unit c in input capacitance (applies to a20-a0, dq15-dq0) v in = 0 8.5 pf c out output capacitance (applies to dq15-dq0, ry/by#) v out = 0 5.5 pf c in2 control pin capacitance (applies to ce#, we#, oe#, wp#/acc, reset#, byte#) v in = 0 12 pf
december 16, 2011 s29jl032j_00_06 s29jl032j 59 data sheet 20. physical dimensions 20.1 ts 048?48-pin standard tsop 3664 \ f16-038.10 \ 11.6.7 package ts/tsr 48 jedec mo-142 (d) dd symbol min nom max a --- --- 1.20 a1 0.05 --- 0.15 a2 0.95 1.00 1.05 b1 0.17 0.20 0.23 b 0.17 0.22 0.27 c1 0.10 --- 0.16 c 0.10 --- 0.21 d 19.80 20.00 20.20 d1 18.30 18.40 18.50 e 11.90 12.00 12.10 e 0.50 basic l 0.50 0.60 0.70 0? --- 8 r 0.08 --- 0.20 n48 notes: 1. controlling dimensions are in millimeters (mm). (dimensioning and tolerancing conform to ansi y14.5m-1982) 2. pin 1 identifier for standard pin out (die up). 3. pin 1 identifier for reverse pin out (die down): ink or laser mark. 4. to be determined at the seating plane -c- . the seating plane is defined as the plane of contact that is made when the package leads are allowed to rest freely on a flat horizontal surface. 5. dimensions d1 and e do not include mold protrusion. allowable mold protusion is 0.15mm (.0059") per side. 6. dimension b does not include dambar protusion. allowable dambar protusion shall be 0.08mm (0.0031") total in excess of b dimension at max. material condition. minimum space between protrusion and an adjacent lead to be 0.07mm (0.0028"). 7. these dimensions apply to the flat section of the lead between 0.10mm (.0039") and 0.25mm (0.0098") from the lead tip. 8. lead coplanarity shall be within 0.10mm (0.004") as measured from the seating plane. 9. dimension "e" is measured at the centerline of the leads.
60 s29jl032j s29jl032j_00_06 december 16, 2011 data sheet 20.2 vbk048?48-pin fbga g1001.2 \ f16-038.25 \ 07.13.10 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls. 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. package vbk 048 jedec n/a 8.15 mm x 6.15 mm nom package symbol min nom max note a --- --- 1.00 overall thickness a1 0.18 --- --- ball height d 8.15 bsc. body size e 6.15 bsc. body size d1 5.60 bsc. ball footprint e1 4.00 bsc. ball footprint md 8 row matrix size d direction me 6 row matrix size e direction n 48 total ball count b 0.33 --- 0.43 ball diameter e 0.80 bsc. ball pitch sd / se 0.40 bsc. solder ball placement --- depopulated solder balls
december 16, 2011 s29jl032j_00_06 s29jl032j 61 data sheet 21. revision history section description revision 01 (january 27, 2010) initial release. revision 02 (june 15, 2010) global changed all references to typical sector erase time from 0.4 sec to 0.5 sec. changed all references to ?secured silicon sector? to ?secured silicon region?. corrected spelling and grammatical errors. product selector guide corrected standard voltage range of 70 ns option from 3.0-3.6v to 2.7-3.6v. connection diagrams added 48-ball fbga connection diagram. pin description changes ?21 addresses? to ?21 address pins?. added clarification that ce#, oe#, we#, byte#, and ry/by# are active low. ordering information added fbga ordering option. added low-halogen, pb-free ordering option. added valid combinations for fbga. word/byte configuration added clarification that byte# must be connected to either the system v cc or ground. secured silicon region added clarification that d7 is the secured silicon factory indicator bit. in figure secured silicon sector protect verify, corrected ?write reset command? to ?secured silicon region exit command?. command definitions corrected ?writing specific addresses and data commands or sequences? to ?writing specific addresses and data sequences?. absolute maximum ratings corrected ?a9, oe#, and reset#? to ?a9 and reset#?. dc characteristics removed oe# from i lit parameter description. removed oe# = 12.5v from i lit test conditions. added 1 mhz to i cc6 and i cc7 test conditions. removed note 1 from i cc6 and i cc7 . test conditions update figure ?test setup? to reflect correct test setup. added note 1 to clarify that input rise and fall times are 0-100%. erase and programming performance changed chip erase typical time from 28 sec to 39 sec. removed note 5. physical dimensions added vbk048 package outline drawing. revision 03 (august 25, 2010) global updated the data sheet designation from advanced information to preliminary. corrected spelling, capitalization, and grammatical errors. simultaneous read/write operations with zero latency clarified that jl032j can be configured as either a top or bottom boot sector device, not both. ordering information corrected typo in valid combinations table from ??, 41, 41? to ??, 41, 42?. clarified that note 1 applies to the packing type column. reset#: hardware reset pin changed ?refer to ac characteristics on page 48? to ?refer to hardware reset (reset#) on page 49?. secured silicon region clarified the secured silicon indicator bit data based on factory and customer lock status. removed forward looking statements regarding factory locking features as they are supported in this device. common flash memory interface (cfi) clarified that once in the cfi query mode, the system must write the reset command to return to reading array data. erase suspend/erase resume commands added clarification that ?it is not recommended to program the secured silicon region after an erase suspend, as proper device functionality cannot be guaranteed.? erase and programming performance added note 5 regarding minimum program and erase cycle endurance.
62 s29jl032j s29jl032j_00_06 december 16, 2011 data sheet pin capacitance changed section title from "tsop pin capacitance" to "pin capacitance". updated values to reflect maximum capacitances for both tsop and bga. removed typical capacitance values. added specific pin clarifications to parameter descriptions. physical dimensions updated the vbk048 package outline drawing. revision 04 (april 7, 2011) global updated the data sheet designation from preliminary to full production (no designation on document). distinctive characteristics corrected "top and bottom boot sectors in the same device" to "top and bottom boot sector configurations available". reset#: hardware reset pin added warning that keeping ce# at v il from power up through the first reset could cause erroneuous data on the first read. reset command clarified that during an embedded program or erase, if dq5 goes high then ry/by# will remain low until a reset is issued. hardware reset (reset#) added note to the ?reset timings? figure clarifying that ce# should only go low after reset# has gone high. revision 05 (august 24, 2011) reset#: hardware reset pin removed warning that keeping ce# at v il from power up through the first reset could cause erroneuous data on the first read. command definitions table added note 17 to clarify additional sector erase commands during time-out period. sector erase command sequence added clarification regarding additional sector erase commands during time-out period. hardware reset (reset#) removed note to the ?reset timings? figure cl arifying that ce# should only go low after reset# has gone high. physical dimensions package drawings updated to latest version. revision 06 (december 16, 2011) global corrected all references in the text to the sector erase time-out period from 80 s to 50 s. word/byte configuration removed the statement ?please note that the byte# pin must be connected to either the system v cc or ground.? section description
december 16, 2011 s29jl032j_00_06 s29jl032j 63 data sheet colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a s erious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semic onductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restriction s on export under the foreign exchange and foreign trade law of japan, the us export administration regulations or the applicable laws of any oth er country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subject to change without notice. this document may contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the informati on in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any ot her warranty, express, implied, or statutory. spansion assume s no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2010-2011 spansion inc. all rights reserved. spansion ? , the spansion logo, mirrorbit ? , mirrorbit ? eclipse?, ornand?, ecoram? and combinations thereof, are trademarks and registered tr ademarks of spansion llc in the united states and other count ries. other names used are for informational purposes only and may be trademarks of their respective owners.

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